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Hi everybody.
I use quartusII 9.1-sp1 and i develop on cyclonne-III board with serial flash memory epcs4 with 16mhz crystal.
But on my development board, when i add some signals-probes for debugging, or other signals, misteriouly :confused: the board not run correctly :confused:
My dev board is buggy randomly after modify shematic and reprogramming memory of FPGA. Modif is very simple i add/sub not-cell and probes.
I try lcell, but it fell like.
What can i do ?
Please, what is entrance and fanout of general logics-cells Into cycIII fpga or Altera cpld ?
Excuse my bad English.
Thank you.
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Hi,
I assume you add some connection to signal, which you would like to see on FPGA pins.
Right ?
Kind regards
GPK
Honored Contributor
