Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to develop a Verilog model for a peak detector?

Develop a Verilog model for a peak detector that finds the maximum value in a sequence of 10-bit unsigned integers. A new number arrives

at the input during a clock cycle when the data_en input is 1. If the new number is greater than the previously stored maximum value, the maximum value is updated with the new number; otherwise, it is unchanged. The stored maximum value is cleared to zero when the reset control input is 1. Both data_en and reset are synchronous control inputs.

Please help, thanks!

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    Homework?

    module peak_detect(
       input  wire       clk,
       input  wire       reset,
       input  wire       data_en,
       input  wire  in,
       output reg   peak );
    always @ (posedge clk)
       if (reset) peak <= 0;
       else if (data_en && (in > peak))
          peak <= in;
    endmodule

    Cheers,

    Alex
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Homework?

    module peak_detect(
       input  wire       clk,
       input  wire       reset,
       input  wire       data_en,
       input  wire  in,
       output reg   peak );
    always @ (posedge clk)
       if (reset) peak <= 0;
       else if (data_en && (in > peak))
          peak <= in;
    endmodule

    Cheers,

    Alex

    --- Quote End ---

    Thanks Alex.... i got it done yesterday... thanks anyway :)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    Homework?

    module peak_detect(
       input  wire       clk,
       input  wire       reset,
       input  wire       data_en,
       input  wire  in,
       output reg   peak );
    always @ (posedge clk)
       if (reset) peak <= 0;
       else if (data_en && (in > peak))
          peak <= in;
    endmodule

    Cheers,

    Alex

    --- Quote End ---

    Hey Alex... do you know how to detect several peaks?