How to develop a Verilog model for a peak detector?

module peak_detect(
   input  wire       clk,
   input  wire       reset,
   input  wire       data_en,
   input  wire  in,
   output reg   peak );
always @ (posedge clk)
   if (reset) peak <= 0;
   else if (data_en && (in > peak))
      peak <= in;
endmodule