Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

How to develop a Verilog model for a peak detector?

Develop a Verilog model for a peak detector that finds the maximum value in a sequence of 10-bit unsigned integers. A new number arrives at the input during a clock cycle when the data_en input is...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Homework? 

module peak_detect(
   input  wire       clk,
   input  wire       reset,
   input  wire       data_en,
   input  wire  in,
   output reg   peak );
always @ (posedge clk)
   if (reset) peak <= 0;
   else if (data_en && (in > peak))
      peak <= in;
endmodule

Cheers,

Alex