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New ContributorHow to design a 1-out-of-3 clock multiplex
Hi!
I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL.
Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. And, I can't cascade two altclkctrl because its input can only be clock pin or PLL's ouput clock.
I'm wondering if there is any way I can design a 1-out-of-3 clock multiplex?
Here is my configuration:
Terasic DE3 (Stratix III) + Quartus 13.1
You can use the Quartus assignment as Global Signal. Steps are as described in this kdb:
