Forum Discussion

OCn's avatar
OCn
Icon for New Contributor rankNew Contributor
5 years ago
Solved

How to design a 1-out-of-3 clock multiplex

Hi! I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL. Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. ...
OCn's avatar
OCn
Icon for New Contributor rankNew Contributor
5 years ago

Hi JonWay,

Thanks for your reply and suggestion.

That Verilog code's function should be OK. And, how should I ensure that the output clock will use the global clock network, as that clock will drive a lot of circuit in our design?

  • OCn's avatar
    OCn
    Icon for New Contributor rankNew Contributor
    5 years ago

    Hi JonWay,

    OK, I understand.

    Thanks for your prompt reply and help!

    I wish you a good day!