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OCn
New Contributor
New ContributorHow to design a 1-out-of-3 clock multiplex
Hi! I'd like to use a clock mux, e.g., altclkctrl, to select one of the 3 clocks generated by a PLL. Unfortunately, I can't use altclkctrl because Stratix III's altclkctrl only provides 2 inputs. ...
You can use the Quartus assignment as Global Signal. Steps are as described in this kdb:
JonWay_altera
Frequent Contributor
Frequent ContributorPerhaps you can consider implementing it in the core logic.
You can refer to: https://courses.cs.washington.edu/courses/cse467/08au/labs/Resources/Recommended%20HDLCoding%20Styles.pdf
Page 56.
You will need to evaluate if this works for you.
OCnNew Contributor
New ContributorHi JonWay,
Thanks for your reply and suggestion.
That Verilog code's function should be OK. And, how should I ensure that the output clock will use the global clock network, as that clock will drive a lot of circuit in our design?
- JonWay_altera
You can use the Quartus assignment as Global Signal. Steps are as described in this kdb:
- OCn
Hi JonWay,
OK, I understand.
Thanks for your prompt reply and help!
I wish you a good day!
