Honored ContributorHello everyone. i'm suppose to create a simple verilog based alarm clock project and the program it to a FPGA board to obtain the output. As i'm a beginner to this and i have no knowledge in programming the verilog code, can anyone guide me through this? I'm excited to learn about verilog. Please guide me. Thanks in advance.:cool:
Honored ContributorHave you tried anything? Have a go, when you get stuck post a more specific problem. Then we can help.
[url]http://vol.verilog.com/ (http://vol.verilog.com/)[/URL]Honored ContributorYou can start by drawing out flow chart on how your alarm project should behave. Then code it. You can use QII Analysis & Synthesis compilation to help check the code syntax. To simulate the functionality, you can use Modelsim Altera Starter edition which is free.
Honored Contributordid you google around see if some potential solution applicable? !!
Honored ContributorHello. I had tried to program an alarm clock with the help of my tutor. But, i'm unable to reset the clock once it is started. Can anyone guide me through this. Thanks In advance.
New ContributorHello. Help me urgently. Does this code you wrote have a schema? And can you briefly explain to me what code is responsible for what. Post the code if you solved the problem with the reset?
Honored ContributorI assume you want to reset the clock from another push button or similar available on your hardware? So, you'll need another input port and some conditional statement to reset your registers.
You already have statements like "min1=0" etc, to provision initial values. You need to repeat these within an always block to re-initialise these values when your reset signal is active. Cheers, Alex
