Forum Discussion
New ContributorHow to create a new component that instantiates a IP variant in PD?
To answer your question can you add the .ip IP variant file directly into the Component Editor file list to create a custom IP?
No, you cannot simply add the .ip IP variant file (created by the IP Catalog) directly to the HDL file list in the Component Editor to create a new custom IP.
The Component Editor is designed to work with HDL files and expects a top-level HDL module. IP variant files generated by the IP Catalog contain metadata and references for the IP core, but are not HDL source files themselves. As a result, Platform Designer does not treat them as synthesizable modules and cannot instantiate them directly in a new custom component.You may need to use alternate approaches for combining HDL and IP Instantiation
1. Use the _hw.tcl Composition Callback to Instantiate IP
- Write a custom _hw.tcl file for your component.
- Use the add_hdl_instance command within a composition or elaboration callback to instantiate the DCFIFO IP (or other IP core) as a child instance in your custom component.
- The IP core must be available in the project (usually generated from IP Catalog).
- You can parameterize the child IP using set_instance_parameter_value.
- This method allows you to wrap HDL logic around IP instances and export interfaces as needed.
Example (simplified):
package require -exact qsys 14.0 set_module_property name my_custom_dc_fifo set_module_property COMPOSITION_CALLBACK composed_component proc composed_component {} { add_hdl_instance my_dcfifo_inst altera_dc_fifo set_instance_parameter_value my_dcfifo_inst WIDTH_IN 128 set_instance_parameter_value my_dcfifo_inst WIDTH_OUT 32 # Export interfaces, connect clocks/resets as needed set_interface_property stream_in EXPORT_OF my_dcfifo_inst.stream_in set_interface_property stream_out EXPORT_OF my_dcfifo_inst.stream_out # Add other logic/interfaces as necessary }
- See Section 3.9. Create a Composed Component or Subsystem for details.
2. Use HDL Wrapper Module and Reference the IP Core
- Create a top-level HDL module (SystemVerilog or VHDL) that instantiates the DCFIFO IP (referencing its generated module name).
- Add this wrapper HDL file to the Component Editor, specifying the top-level ports and interfaces.
- The IP variant and supporting files must be present in the project directory.
- This approach is more manual but sometimes simpler for small projects.
3. Use Fileset and Elaboration/Composition Callbacks for Parameterized HDL + IP
- For more advanced setups, use fileset callbacks and elaboration/composition procedures in your _hw.tcl to dynamically select files, interfaces, and parameters based on the component's configuration.
- This is required if your component’s HDL or child IPs change based on user parameters.
Super ContributorYour understanding of callback exclusivity is correct: if a component uses COMPOSITION_CALLBACK, Platform Designer does not allow ELABORATION_CALLBACK on the same component.
However, this does not mean that embedding IP in a custom component is impossible when dynamic interface control is needed. Instead, you need to select one supported architecture:
Path A (Recommended for dynamic hide/show interfaces):
Use a static or generated custom component with ELABORATION_CALLBACK, and instantiate child IP using add_hdl_instance.
Path B (Composed subsystem style):
Use COMPOSITION_CALLBACK with add_instance, and handle conditional interface/export decisions within the composition flow (without using elaboration callback).
The limitation is that you cannot use both callbacks in a single component—not that you cannot embed IP with dynamic behavior.
Regarding your Option 2 issue:
Here is a practical, GUI-first troubleshooting flow:
- Start with a minimal example: Create one custom component, one child IP, and a parameter toggle (e.g., for hiding an interface).
- Choose a single model: Use either the "Composed" or "Static/Generated" approach—do not mix assumptions from both in one test.
- Monitor Instantiation Messages: In Component Instantiation, review and resolve all warnings before regenerating.
- Sync checks: Use IP file vs. component synchronization warnings to catch stale parameterization after edits.
- Validate parameter toggling: Re-run validation for each parameter value (toggle ON/OFF) and confirm the presence or absence of the interface as expected.
- Debug wrapper-based flows: If issues occur, first verify the top-level entity name, port directions and widths, and file compile order, as these are common sources of problems.
- Check child IP embedding: Ensure each instance has a unique variation name and is regenerated after parameter changes.
- Incremental complexity: Export one interface at a time. Start with clock/reset, then add data buses, increasing complexity step-by-step.
