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Honored ContributorHow to constrian system clock and tranceiver ref clock?
I am using ArriaGX, there are two clocks input to my FPGA. One is the system clock in and another is the GXB's reference clock.
My SDC file is as below: create_clock -period 10.000 -name clkin -waveform {0 5} [get_ports {refclk}] create_clock -period 10.000 -name clkin -waveform {0 5} [get_ports {clkin}] derive_pll_clocks There are several warnings after compilation: Info: Reading SDC File: 'src/my.sdc' Warning: Overwriting existing clock: clkin Warning: The master clock for this clock assignment could not be derived. Clock: refclk~refclk_div|clkout was not created. Warning: No clocks found on or feeding the specified source node: refclk~refclk_div|inclk Warning: Ignoring clock spec: inst9|u_XCVR_TX_1Ch|alt2gxb_component|channel_quad[0].pll0|clkout Reason: Clock derived from ignored clock: refclk~refclk_div|clkout. Clock assignment is being ignored. Warning: Ignoring clock spec: inst9|u_XCVR_TX_1Ch|alt2gxb_component|channel_tx[0].transmit|clkout Reason: Clock derived from ignored clock: inst9|u_XCVR_TX_1Ch|alt2gxb_component|channel_quad[0].pll0|clkout. Clock assignment is being ignored. Warning: PLL cross checking found inconsistent PLL clock settings: Warning: Node: refclk~refclk_div|clkout was found missing 1 generated clock that corresponds to a base clock with a period of: 10.000 How to deal with these warning issue?
