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Altera_Forum's avatar
Altera_Forum
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14 years ago

How to constrian system clock and tranceiver ref clock?

I am using ArriaGX, there are two clocks input to my FPGA. One is the system clock in and another is the GXB's reference clock. My SDC file is as below: create_clock -period 10.000 -...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Isn't there a typo in your .SDC file though:

--- Quote Start ---

create_clock -period 10.000 -name refclk -waveform {0 5} [get_ports {refclk}]

create_clock -period 10.000 -name clkin -waveform {0 5} [get_ports {clkin}]

derive_pll_clocks

--- Quote End ---

Cheers,

Dave