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Altera_Forum
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14 years ago

How to constrian system clock and tranceiver ref clock?

I am using ArriaGX, there are two clocks input to my FPGA. One is the system clock in and another is the GXB's reference clock. My SDC file is as below: create_clock -period 10.000 -...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You use the same -name for both clocks. The second one overrides the first, so now refclk is no longer constrained. With it not constrained, the transceiver it drives that is constrained by derive_pll_clocks no longer works. Give the first one a distinct name and I think it will work.