How to constrain Jtag signals of Cyclone 4 FPGA?

Question

I constrained all I/Os of my FPGA Cyclone 4 device.

But still it shows unconstrained path for jtag signals:-

altera_reserved_tdi,altera_reserved_tdo,altera_reserved_tms,altera_reserved_tck.

Can I set Jtag signals as false path?

How to constrain these signals?

rahul_s_intel1 · Answer

Hi , Those signals are reserved signals.Rs

sk_va · Answer

These are reserved signals.But Timing analysis shows unconstrained paths for these pins.How to solve this?

knug · Answer

Same question I have.
Timing STA analysis showed

no output delay : altera_reserved_tdo
no input delays : altera_reserved_tms, altera_reserved_tck &amp; alrera_reserved_tdi

How do we constrain them ?

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