Forum Discussion
SK_VA
Occasional Contributor
Occasional ContributorHow to constrain Jtag signals of Cyclone 4 FPGA?
I constrained all I/Os of my FPGA Cyclone 4 device. But still it shows unconstrained path for jtag signals:- altera_reserved_tdi,altera_reserved_tdo,altera_reserved_tms,altera_reserved_tck. Can I ...
SK_VAOccasional Contributor
Occasional ContributorThese are reserved signals.But Timing analysis shows unconstrained paths for these pins.
How to solve this?
Knug
Contributor
ContributorSame question I have.
Timing STA analysis showed
- no output delay : altera_reserved_tdo
- no input delays : altera_reserved_tms, altera_reserved_tck & alrera_reserved_tdi
How do we constrain them ?
