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SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

How to constrain Jtag signals of Cyclone 4 FPGA?

I constrained all I/Os of my FPGA Cyclone 4 device. But still it shows unconstrained path for jtag signals:- altera_reserved_tdi,altera_reserved_tdo,altera_reserved_tms,altera_reserved_tck. Can I ...
SK_VA's avatar
SK_VA
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

These are reserved signals.But Timing analysis shows unconstrained paths for these pins.

How to solve this?

Knug's avatar
Knug
Icon for Contributor rankContributor
5 years ago

Same question I have.

Timing STA analysis showed

  • no output delay : altera_reserved_tdo
  • no input delays : altera_reserved_tms, altera_reserved_tck & alrera_reserved_tdi

How do we constrain them ?