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NTA's avatar
NTA
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6 months ago
Solved

How to configure Dual Compressed Images on MAX10 without IP core?

Hello,

we have a PCB with a MAX10 FPGA (M50SAE144I7G) and would like to make use of the dual configuration feature.

The PCB features a switch that pulls the FPGA's dedicated config_select pin to HIGH/LOW.

Our plan is, to use two slightly different images (same design, different slew rate and termination settings) for demonstration purposes in a lab course.

To our understanding this should be possible without using the dual config IP core as we do not need to switch images while the FPGA is running.

However, we cannot find any useful instructions on how to set this up. The "MAX 10 FPGA Configuration User Guide" leads to a dead end:
"The .sof can be added through Input files to convert list and you can add up to two .sof files."

After adding the first .sof file both the "Add Sof Page" and "Add File..." buttons are grayed out.

We are using various versions of Quartus Prime Lite Edition (mainly 19.1 and 24.1). Is this feature simply not available in the Lite Edition or are we missing something?

Many thanks in advance!

Kind regards,

Nils

Hdl
  • WZ2's avatar
    WZ2
    6 months ago

    Hi there，

    ​

    What you are encountering now seems to be a config issue. It looks like the previous problem with sof -> pof conversion has been resolved. Unfortunately, the root cause of the failure is still unclear. So I would like to further confirm the following:

    1. Loading the standalone sof file included in the pof works fine, right?
    2. In step 6, the CPF mode is set to Internal Configuration.
    3. Does the Programmer show any specific error messages?
    4. If you reduce the JTAG speed to 6 MHz in the Programmer, does it help to resolve the issue?

    Best regards,

    WZ


8 Replies

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    6 months ago
    As far as I see it's required to have .sof files compiled for dual compressed configuration mode to be able to assign more than one page in .pof generation.

    Respectively you need to import at least a dummy dual configuration controller to your design.
    • NTA's avatar
      NTA
      Icon for New Contributor rankNew Contributor
      6 months ago

      @FvM thanks for the hint!

      Okay, so in my individual projects under
      Assignments -> Device -> Device and Pin Options... -> Configuration

      I selected

      • Configuration Scheme: Internal Configuration
      • Configuration Mode: Dual Compressed Images (512Kbits UFM)

      and then tried to recompile the project which lead to:

      Error (169130): Configuration mode specified as Remote but remote update block is not found in design

      @FvM wrote:
      Respectively you need to import at least a dummy dual configuration controller to your design.

      How is this done?

      We were hoping the config_sel pin would allow for a simple solution along the lines of "simply flashing two images at once in the programmer" and not having to worry about anything in the actual designs.

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    6 months ago

    Hi Nils,

    If u wanna put two sof into one pof, u have to use the dual config ip in your design.

    Best regards,

    WZ


  • NTA's avatar
    NTA
    Icon for New Contributor rankNew Contributor
    6 months ago

    Hello, thank you all for your help.

    Unfortunately, I still cannot get this to run as expected.

    Here's what I have tried so far:

    1. Assignments -> Device -> Device and Pin Options... -> Configuration
      - Configuration Scheme: Internal Configuration
      - Configuration Mode: Dual Compressed Images (512Kbits UFM)

    2. Add dual config IP core (as VHDL like the project itself)
    3. Added the IP core's files:
      - set_global_assignment -name QIP_FILE dual_config/synthesis/dual_config.qip
      - set_global_assignment -name VHDL_FILE dual_config/synthesis/dual_config.vhd -library dual_config
    4. Added a dummy dual config in my main VHDL file:
      component dual_config
      end component;
      ...
      u_dual_config : dual_config;
    5. Compile the design to get a SOF file
    6. In convert program files:
      - add two of those SOF files as separate pages
      - create a POF file
    7. Open programer:
      - load that POF file
      - select program/configure
      - Start -> Unsuccessful (0%)

      Have I overlooked a critical step?
    • NTA's avatar
      NTA
      Icon for New Contributor rankNew Contributor
      6 months ago

      I have set both projects to compressed:
      Assignments -> Device -> Device and Pin Options... -> Configuration
      - Configuration Scheme: Internal Configuration
      - Configuration Mode: Dual Compressed Images (512Kbits UFM)

      And I have also selected CFM0 and CFM1 in the programmer.

      Thank you for the link!
      I will definitely take a look at the training, even though it seems to go far beyond what we are trying to achieve.

  • WZ2's avatar
    WZ2
    Icon for Frequent Contributor rankFrequent Contributor
    6 months ago

    Hi there，

    ​

    What you are encountering now seems to be a config issue. It looks like the previous problem with sof -> pof conversion has been resolved. Unfortunately, the root cause of the failure is still unclear. So I would like to further confirm the following:

    1. Loading the standalone sof file included in the pof works fine, right?
    2. In step 6, the CPF mode is set to Internal Configuration.
    3. Does the Programmer show any specific error messages?
    4. If you reduce the JTAG speed to 6 MHz in the Programmer, does it help to resolve the issue?

    Best regards,

    WZ


    • NTA's avatar
      NTA
      Icon for New Contributor rankNew Contributor
      6 months ago

      Hello @WZ2 ,

      thank you for your help!

      Reducing the JTAG speed was indeed the last missing puzzle piece.

      Everything is working as expected now.

      Kind regards,

      Nils