Honored ContributorI have this VHDL code within my architecture:
architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); I know that I can use Vector Waveform File to monitor my waveform of INPUT and OUTPUT pins. Would it be possible to monitor my signal, such as butterfly8_r_Z1 in the architecture? If so, how to do it? Thanks
Honored ContributorSynthesize the design. In the .vwf Insert Node or Bus, and then locate that signal. Note that it you're doing a timing simulation, i.e. the design has been synthesized, then a lot of signals get synthesized away. That's not to say they're removed, they just don't exist as a point you can "see". For example, if your signal was between two AND gates, then they might get merged into a single LUT, and the actual signal doesn't exist, but the behavior of the two AND gates does. If it's a register, then you should be in good shape.
I would recommend just doing a functional simulation. This can be chosen in Assignments -> Settings -> Simulation. Be sure to read the Quartus II handbook on simulations: http://www.altera.com/literature/hb/qts/qts_qii53017.pdfHonored ContributorWhat should I select in the FILTER? For input and output pins, it is normally PINS:ALL. What about for the signal within architecture?
Honored ContributorFor example, I have a simple code:
Library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity orgate2 is port( out1 : out std_logic_vector(3 downto 0) ); end orgate2; architecture add of orgate2 is signal temp : std_logic_vector (3 downto 0); begin temp <= "1111"; out1 <= temp - "1100"; end add; I want to check the signal temp. Then, I go to node finder and select design entry (all names). On the list, I have selected the node temp. Now, the temp node is on my waveform list and I would like to perform simulation. However, when I performed the simulation, the temp node no longer exist and gone. Anyone can help?Honored ContributorFirst you're probably doing a timing simulation, which means it's after synthesis, so temp would no exist because it gets synthesized out.
Second, even if doing a functional simulation, temp isn't doing anything. Your simulating 1111 - 1100. That is a constant. Note that this is not sequential code but parallel, so all things are happening at once. Basically the code will have a constant output of out1 getting 0011. There's no logic in the design.Honored ContributorFor functional sims, use pre-synthesis. For timing use post-fit. THe other ones work too. For example, if you choose post-fit and select a register, and that node name exists in the pre-synthesis, it will use it in the functional simulation. Worst thing that happens is you choose a node that doesn't exist in your simulation and have to go back and find one that does. You'll quickly get an understanding of what's available.
Honored ContributorI am using Functional Simulation. Sorry, I am quite new so couldn't really understand. Would you mind to give a simple exampe. So that I can check my temp node?
Honored Contributortemp is a constant, so there's no point in "checking it". It will always be removed during synthesis since it doesn't do anything. I really don't know what you're trying to do, but would suggest getting a book on HDL design. Probably the best thing when getting started is to think in terms of schematics, not code. If you have a constant in a schematic that subtracts another constant, the result is a constant.
(And as I said, this isn't sequential, where temp gets a value first. You could switch the order of these two statements and it's the same thing. )Honored ContributorI got what you mean and that was just a simple example.
Actually, I want to check the waveform of a signal declared within the architecture. I am actually designing a system where there are too many input and output ports. Therefore, I am thinking to move all my input and output ports within the architecture. Note that, I don't have to implement this to hardware but I would like to try it and run using VHDL. So, what I am actually doing is setting the input as constant. For the output, I would like to check the signal waveform. Thats why I want to do such an operation. Could you suggest some methods to do this?Honored Contributorcwjcwjcwj,
You can use the Vector Waveform to do that checking, but it is normally used to check (functional or timing simulation) sequential behaviours, not just combinational. However, to check the output signal, you must to add to your Vector Waveform file the inputs and output of your architecture. To add those inputs/outputs (or signals) do: Edit -> Insert -> Insert Node or Bus after, just choose the pins as Rysc has already said. You must to set the configuration of your input and after save the file. Make the compilation and then verify the output pins. My best, higorHonored ContributorThanks, Higor.
I am actually writing VHDL for 128 points FFT and I am using floating point (32 bits precision). So, I need 128*32 pins for inputs and 128*32 pins for outputs. I am sure none of the existing device supports so many pins. I believe there are many ways to solve it. Maybe Parellel to Serial converter. What if I am writing a test bench? Any comments and suggestions?
