Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

How to check signal waveform.

I have this VHDL code within my architecture: architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Synthesize the design. In the .vwf Insert Node or Bus, and then locate that signal. Note that it you're doing a timing simulation, i.e. the design has been synthesized, then a lot of signals get synthesized away. That's not to say they're removed, they just don't exist as a point you can "see". For example, if your signal was between two AND gates, then they might get merged into a single LUT, and the actual signal doesn't exist, but the behavior of the two AND gates does. If it's a register, then you should be in good shape.

I would recommend just doing a functional simulation. This can be chosen in Assignments -> Settings -> Simulation. Be sure to read the Quartus II handbook on simulations:

http://www.altera.com/literature/hb/qts/qts_qii53017.pdf