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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to check signal waveform.

I have this VHDL code within my architecture: architecture first of butterfly8 is signal butterfly8_r_Z1, butterfly8_r_Z2, butterfly8_r_Z3, butterfly8_r_Z4: std_logic_vector(31 downto 0); ...
Altera_Forum's avatar
Altera_Forum
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16 years ago

I got what you mean and that was just a simple example.

Actually, I want to check the waveform of a signal declared within the architecture.

I am actually designing a system where there are too many input and output ports. Therefore, I am thinking to move all my input and output ports within the architecture. Note that, I don't have to implement this to hardware but I would like to try it and run using VHDL. So, what I am actually doing is setting the input as constant. For the output, I would like to check the signal waveform. Thats why I want to do such an operation. Could you suggest some methods to do this?