How to check signal waveform.

For example, I have a simple code:

Library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity orgate2 is

port(

out1 : out std_logic_vector(3 downto 0)

);

end orgate2;

architecture add of orgate2 is

signal temp : std_logic_vector (3 downto 0);

begin

temp <= "1111";

out1 <= temp - "1100";

end add;

I want to check the signal temp. Then, I go to node finder and select design entry (all names). On the list, I have selected the node temp. Now, the temp node is on my waveform list and I would like to perform simulation. However, when I performed the simulation, the temp node no longer exist and gone. Anyone can help?