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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to break up long FIR DSP block chain?

Dear all,

I finally managed to infer a FIR filter (systolic per pair of two located in one DSP block) using DSP blocks with all relevant registers inside the DSP blocks (on my Arria V StarterKit using 5AGXFB3H4F35C4).

Now I see that the maximal number of DSP blocks I can use is 28 or 56 FIR taps (which just fits in the upper half of the device using one long column). Trying to go to larger filters ends up in failing to place the design (although using a global clock).

My questions:

Is it possible to split up this kind of filters to use more than one column of DSP blocks? if yes, how? (I tried by means of defining a logic lock area, but didn't succeed so far, the fitter does not care about the logic lock).

Regards,

Peter

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    cant you just put some registers between multiplier stages in the FIR, to allow it to route between columns?

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    as a general workaround, have you thought of using half multipliers by pre adding (if your filter is symmetric)

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    @Tricky

    Actually, my filter is built in systolic way with systolic registers every two taps (after each DSP block), so register are basically already there. I don't want to spend additional latency, so I'm searching a way to tell the synthesizer to do it with the given architecture.

    @kaz

    Unfortunately, the filter is not symmetric. Parameters are loaded from the outside, as I have virtually unlimited number of parameter sets.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    why dont you want to add extra latency? the latency will not affect the throughput.

    This sounds like you are using DSP instantiations directly to get the design at a low level, rather than infering the multipliers??
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    In the dsp sense you can break any filter into a cascade (or addition) of smaller filters using z domain algebra. If that is of use then I can tell you how.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    why dont you want to add extra latency? the latency will not affect the throughput. This sounds like you are using DSP instantiations directly to get the design at a low level, rather than infering the multipliers??

    --- Quote End ---

    No it isn't. Just the other way round. Everything is inferred in that filter.

    Now I wonder, why the tools are not able to place the systolic registers outside the DSP when going over to a new column of DSP blocks and inside in all other cases. Instead, it just says "can't fit".