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Altera_Forum's avatar
Altera_Forum
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11 years ago

How to break up long FIR DSP block chain?

Dear all, I finally managed to infer a FIR filter (systolic per pair of two located in one DSP block) using DSP blocks with all relevant registers inside the DSP blocks (on my Arria V StarterKi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

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why dont you want to add extra latency? the latency will not affect the throughput. This sounds like you are using DSP instantiations directly to get the design at a low level, rather than infering the multipliers??

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No it isn't. Just the other way round. Everything is inferred in that filter.

Now I wonder, why the tools are not able to place the systolic registers outside the DSP when going over to a new column of DSP blocks and inside in all other cases. Instead, it just says "can't fit".