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Altera_Forum
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11 years ago@Tricky
Actually, my filter is built in systolic way with systolic registers every two taps (after each DSP block), so register are basically already there. I don't want to spend additional latency, so I'm searching a way to tell the synthesizer to do it with the given architecture. @kaz Unfortunately, the filter is not symmetric. Parameters are loaded from the outside, as I have virtually unlimited number of parameter sets.