Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

How to avoid those annoying ripple/gated clocks warning in Quartus2?

Since the system clock on board is 50MHz high and in my design I need 1KHz or even lower freq clock, I’ve written a clock divider implemented by a counter, with it’s output to drive other modules. Every time I compile the design Quartus2 always complain with following warnings.

Is there any way to fix them? I know it will need carefully global clock design, but don’t know how to get that…

Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew

Info: Detected ripple clock "key_debounce:inst9|keyout" as buffer

Info: Detected ripple clock "key_debounce:inst10|keyout" as buffer

Info: Detected ripple clock "tb_pll:inst5|div_10m:inst8|clkout" as buffer

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The Quartus software handbook has a chapter about design guidelines that briefly discusses the problem of ripple clocks and has suggestions how to handle it. The general suggestion, you'll also find frequently in this forum, is to use clock enables instead of divided clocks. That means, the output of the clock divider is a signal with a frequency of 1 kHz and a width of 1 clock period (20 ns in this case). You can use it as an enable signal inside the clock edge sensitive process for those actions to be scheduled once per ms.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    feed the 50MHz to all registers. For slow side use clkenable to control processing at the required rate.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    The Quartus software handbook has a chapter about design guidelines that briefly discusses the problem of ripple clocks and has suggestions how to handle it. The general suggestion, you'll also find frequently in this forum, is to use clock enables instead of divided clocks. That means, the output of the clock divider is a signal with a frequency of 1 kHz and a width of 1 clock period (20 ns in this case). You can use it as an enable signal inside the clock edge sensitive process for those actions to be scheduled once per ms.

    --- Quote End ---

    Thanks for guiding me the direction!