How to avoid those annoying ripple/gated clocks warning in Quartus2?

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The Quartus software handbook has a chapter about design guidelines that briefly discusses the problem of ripple clocks and has suggestions how to handle it. The general suggestion, you'll also find frequently in this forum, is to use clock enables instead of divided clocks. That means, the output of the clock divider is a signal with a frequency of 1 kHz and a width of 1 clock period (20 ns in this case). You can use it as an enable signal inside the clock edge sensitive process for those actions to be scheduled once per ms.

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Thanks for guiding me the direction!