How To Avoid GND Synthesized As Routed Net?

I have a net that is getting synthesized as a fixed logic '0' value and then routed to 900+ logic element endpoints in the design. This net is named "~GND" and does not exist in the Verilog source code. I would like to change that to a local fixed value instead so that I can clear up many routing lanes to improve the timing performance of the design.

The source code for one 8-bit counter that uses this ~GND net sets some of the counter bits to '1' and some of the counter bits to '0' as can be shown in the source code snippet below:

lpm_counter new_trig (
   .aclr(reset_in),
   .cout(new_trig_cout),
   .cnt_en(!new_trig_out[7]),
   .clock(clk_sensor_out),
   .data(8'b01010101),	
   .sload(rst_cvc_pulse),
   .q(new_trig_out[7:0])
   );
	defparam
   new_trig.lpm_width = 8,	
   new_trig.lpm_direction = "DOWN";

In the resulting synthesized version of this counter, the counter bits that are preset to '1' get a local fixed value, but the counter bits that are preset to '0' get connected to this ~GND net as shown in the screen capture below.

Has anybody else had this happen in the synthesis? If so, is there a way to get force the synthesis tool to use a local fixed value instead of routing a net with a fixed value?

Thanks!

John