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JLevi1's avatar
JLevi1
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8 years ago

How To Avoid GND Synthesized As Routed Net?

I have a net that is getting synthesized as a fixed logic '0' value and then routed to 900+ logic element endpoints in the design. This net is named "~GND" and does not exist in the Verilog source co...
JLevi1's avatar
JLevi1
Icon for New Contributor rankNew Contributor
8 years ago

Hmm, pasting the screenshot into the forum post is not working for me. I cannot see the image using Firefox browser. I could see the screenshot fine before submitting but then it disappears after submitting. As a result, I am attaching the screenshot image to his 3rd post as a file.