Forum Discussion

JLevi1's avatar
JLevi1
Icon for New Contributor rankNew Contributor
7 years ago

How To Avoid GND Synthesized As Routed Net?

I have a net that is getting synthesized as a fixed logic '0' value and then routed to 900+ logic element endpoints in the design. This net is named "~GND" and does not exist in the Verilog source co...
JLevi1's avatar
JLevi1
Icon for New Contributor rankNew Contributor
7 years ago

I referred to a screen shot on the previous post. I pasted the screen shot into the post but I see that it disappeared in the final version of my post. I will attempt to paste the screen shot image in this second post.