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JLevi1's avatar
JLevi1
Icon for New Contributor rankNew Contributor
8 years ago

How To Avoid GND Synthesized As Routed Net?

I have a net that is getting synthesized as a fixed logic '0' value and then routed to 900+ logic element endpoints in the design. This net is named "~GND" and does not exist in the Verilog source co...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
8 years ago

Whenever you hardcode any port/signal / register to a fixed value, the compiler will either tie the signals in question to VCC or GND or ~GND. This cannot be avoided. The other way is to have a register with this value and then connect this register to the port/signal in question. But you are just moving the VCC/GND tie to another level.