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Altera_Forum's avatar
Altera_Forum
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16 years ago

How do I prevent logic from being synthesized away?

I am using Quartus II 9.1 SP2. I have a VHDL design with thousands of electrical noise generators in it. The noise generators have only control inputs, no outputs. When I compile the model, all of the noise generators are synthesized away. This occurs even though I have assigned the VHDL KEEP attribute to latch outputs in the noise generators.

How do I prevent the noise generators from being synthesized away? There are so many generators that creating a dummy output from each of them, ORing the dummy outputs together, and running the OR output to a pin (or virtual pin) is not practical.

Thanks!

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    try the online help at altera web site or quratus online help it will lead you to this :

    --- Quote Start ---

    preserve VHDL Synthesis Attribute

    There are two important limitations of the preserve synthesis attribute:

    It prevents a register from being inferred as a state machine.

    It does not preserve fanout-free registers. Use the noprune synthesis attribute to prevent Analysis & Synthesis from removing fanout-free registers.

    You cannot use this synthesis attribute for registers that have no fan-out.

    To use the preserve synthesis attribute, you must first declare the attribute in the local scope or import its declaration from the altera_syn_attributes package in the altera library. You can then use an attribute specification to associate the attribute with a signal or variable that infers a register in your design. For example, in the following code, the attribute declaration declares the preserve attribute as a boolean object in the local scope, and the attribute specification associates the preserve synthesis attribute with the signal reg1:

    signal reg1: stdlogic;

    attribute preserve: boolean;

    attribute preserve of reg1: signal is true;

    You can also set the preserve synthesis attribute on an entity or architecture, causing Analysis & Synthesis to preserves all registers in the entity or architecture, except registers that infer state machines.

    --- Quote End ---