How do I prevent logic from being synthesized away?

try the online help at altera web site or quratus online help it will lead you to this :

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preserve VHDL Synthesis Attribute

There are two important limitations of the preserve synthesis attribute:

It prevents a register from being inferred as a state machine.

It does not preserve fanout-free registers. Use the noprune synthesis attribute to prevent Analysis & Synthesis from removing fanout-free registers.

You cannot use this synthesis attribute for registers that have no fan-out.

To use the preserve synthesis attribute, you must first declare the attribute in the local scope or import its declaration from the altera_syn_attributes package in the altera library. You can then use an attribute specification to associate the attribute with a signal or variable that infers a register in your design. For example, in the following code, the attribute declaration declares the preserve attribute as a boolean object in the local scope, and the attribute specification associates the preserve synthesis attribute with the signal reg1:

signal reg1: stdlogic;

attribute preserve: boolean;

attribute preserve of reg1: signal is true;

You can also set the preserve synthesis attribute on an entity or architecture, causing Analysis & Synthesis to preserves all registers in the entity or architecture, except registers that infer state machines.

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