How do I disable setup/hold violation errors?

You can just skip timing analysis for transfers between asynchronous clock domains. In your .sdc file either put clocks in separate clock groups or set false path between them. For example:

set_clock_groups -asynchronous -group  -group 

set_false_path -from  -to 
set_false_path -from  -to 

I already did that. This takes care of SDC but doesn't fix the problem with the post-fit simulation.

false paths in sdc means just that at any level. It must you got something else violating timing. I suggest you use fifo instead of your two stage synchroniser.

A FIFO isn't an appropriate solution. The problem isn't with the design, which works fine in real hardware. This is purely a simulation annoyance. A FIFO wont do anything anyway, since internally the FIFO uses the same synchronization chain mechanism.

I am not sure about your description, which tool is reporting tSU/tH violation. Is it Modelsim or quartus?

It's ModelSim I'm using for the simulation.

Does Modelsim report tSU/tH timing violation?

No modelsim does simulation and doesn't do a timing a violation as a error. I may be corrected though by someone else but this is my observation

TrueBlue,