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Altera_Forum
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14 years ago

How do I disable setup/hold violation errors?

I'm simulating a design with ModelSim-Altera. The design has two clock domains and I'm using two-stage synchronizers on data that crosses between the clock domains. Because the two clocks are close i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

You can just skip timing analysis for transfers between asynchronous clock domains. In your .sdc file either put clocks in separate clock groups or set false path between them. For example: 

set_clock_groups -asynchronous -group  -group
or 

set_false_path -from  -to 
set_false_path -from  -to