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Altera_Forum
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14 years ago

How do I disable setup/hold violation errors?

I'm simulating a design with ModelSim-Altera. The design has two clock domains and I'm using two-stage synchronizers on data that crosses between the clock domains. Because the two clocks are close i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

false paths in sdc means just that at any level. It must you got something else violating timing. I suggest you use fifo instead of your two stage synchroniser.