how can i fix this problem ? Error (10170): Verilog HDL syntax error at adc.v(2) near text ";"; expecting ".", or an identifier the coding are for ADC implementation on FPGA.

Hi,

You have written code in VHDL HDL & saved that with verilog extension (*.v), just perform 'Save As..' & save the new file with (*.vhd)extension & remove this abc.v file from project.

Regards,

Vicky

Hi,

Have you resolved the issue?

May I know any update?

Regards,

Vicky