How can I fix issue with JTAG programming mode?

When I was working with my project I’ve got a problem. In the project NIOS II software was loaded from EPCS device into DDR II memory chip. ELF was converted to HEX by the following script:

#! /bin/sh
# $1 - Path to *.sof
# $2 - Path to *.elf
sof2flash --input $1 --output hw.flash --epcs --verbose
elf2flash --input $2 --output sw.flash --epcs -A hw.flash --verbose
nios2-elf-objcopy -I srec -O ihex sw.flash sw.hex

JIC file was created by the dialog window “Convert programming File” with following settings:

I made some changes in my QSys project, regenerated it and started full compilation process in Quartus II software, but I forgot to update HEX according to new changes and I got incorrect JIC file. I loaded this file into EPCS device on my PCB and it stopped working properly. I corrected my mistake and tried to load JIC file again, but I got the error message in Quartus II console window. Quartus version is 14.0.2 build 243.

I erased EPCS device via Active Serial mode, but this problem appeared again and I could not fix PCB workability. I can’t load JIC via JTAG mode, but I can still use «Auto detect» button in «Programmer» window and it gets correct information about FPGA device.