Help With Creating Flip Flops from Logic Gates

Hi,

I am new to VHDL and am taking this course in my university this semester. I need help with one of the questions from the Laboratory Manual.

Students are required to create the following flip-flops (RS, JK, D Flatch, D) using the combination of basic logic gates. Let's pick D Latch, I am sure I can handle the rest by myself.

Initially, we were required to create the VHDL code for the basic logic gates (AND, OR, NOT, XOR and so on). This is not an issue. Here is an example for AND gate.

-- VHDL code for AND gate
library ieee;
use ieee.std_logic_1164.all ;
entity andgate is 
	port(in1, in2: in std_logic;
		 out1: out std_logic);
end entity andgate;
architecture behavior of andgate is
begin
	out1 <= in1 and in2;
end architecture behavior;

The next part is to create the flip-flops. Now, I am able to create the Block Diagram File (.bdf) for D latch and then convert it to VHDL (File > Create/Update > Create HDL Design File for Current File). However, we are actually required to make use of the logic gates that we have created earlier, so I suspect this must have something to do with using components, port map, etc. I need help with this part.

Any help is greatly appreciated, you don't have to post the solution here (I am here to learn not to cheat), just please help me get started in the right direction. Thanks.