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Altera_Forum
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14 years ago

Help With Creating Flip Flops from Logic Gates

Hi, I am new to VHDL and am taking this course in my university this semester. I need help with one of the questions from the Laboratory Manual. Students are required to create the followi...
Altera_Forum's avatar
Altera_Forum
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14 years ago

follow figure 7 of pdf file. I know it does not have enable input. You can leave that for next step. You may for example AND clk and enable but quartus wouldn't be happy as this tool is meant for fpgas and discourages clk gating.

Fig 7 is straighforward set of 6 nand gates each with 3 inputs. Give names to all the nodes and start gating them with not and