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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help With Creating Flip Flops from Logic Gates

Hi, I am new to VHDL and am taking this course in my university this semester. I need help with one of the questions from the Laboratory Manual. Students are required to create the followi...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Obviously this is an exercise for ASIC design. To design flips there are several structures.

D flipflops with clear/reset will impress your professor, so I have attached a file. Look at figure 7 I think that structure is easy to implement directly as a set of "NOT AND" of three inputs.

I haven't done ASIC and will appreciate your feedback work. May be you will need some delays on the feedback paths...