Help! Question about adder implementation!

Hi,

I am try to build and test a very large adder, as my previous try have meet the quartus software constraints, my new way to do that is this:

I write a basic logic for full adder, than a 4 bit adder consist 4FAs, and a large adder consist 500 4 bit adders. Here are the code:

For FA:

library ieee;

use ieee.std_logic_1164.all;

entity FA is

port(a, b : in std_logic;

cin : in std_logic;

cout : out std_logic;

sum : out std_logic);

end entity FA;

architecture df_FA of FA is

begin

cout <= (a AND b) OR (cin AND (a OR b));

sum <= a xor b xor cin;

end architecture df_FA;

For 4 bit adder:

library ieee;

use ieee.std_logic_1164.all;

entity RCA is

port(

a, b : in std_logic_vector(3 downto 0);

cout : out std_logic;

cin : in std_logic;

sum : out std_logic_vector(3 downto 0)

);

end entity RCA;

architecture struct_RCA of RCA is

component FA is

port(

a, b : in std_logic;

cin : in std_logic;

cout : out std_logic;

sum : out std_logic);

end component;

signal carry: std_logic_vector(3 downto 0);

begin

RippleCarryAdder:

for i in 0 to 3 generate

FAs: entity work.FA

PORT MAP (

a=>a(i),

b=>b(i),

cin=>cin,

cout=>carry(i),

sum=>sum(i)

);

End generate;

cout<=carry(3);

end architecture struct_RCA;

For large adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE IEEE.numeric_std.ALL;

entity CA is

generic (

nblocks: integer := 500;

vsize : integer := 2000

);

Port (

a, b : in STD_LOGIC_VECTOR(vsize-1 downto 0);

sum : out std_logic_vector(vsize - 1 downto 0)

);

end entity CA;

architecture Behavioral of CA is

signal carry : STD_LOGIC_VECTOR(nblocks downto 0);

begin

carry(0)<='0';

adders : for i in 1 to nblocks generate

adder : entity work.RCA

port map(

cin => carry(i-1),

a => a(4*i-1 downto 4*(i-1)),

b => b(4*i-1 downto 4*(i-1)),

sum => sum(4*i-1 downto 4*(i-1)),

cout => carry(i)

);

end generate;

end architecture Behavioral;

I haven't finish the clock and shift input part, and the code so far pass the compile and synthesis. However when I try do to compliation in quartus, a error "Error: Can't place 6000 pins with 2.5 V I/O standard because Fitter has only 342 such free pins available for general purpose I/O placement" poped up. and compliation stopped.

And also in the summary, it said ony 29xx logic element have used, one of my contril signal(a,b or sum) have 500*4=2000bits long, three of them should have 6000 logic elements at least, why is that? Is that becasuse of I haven't finish the shift input part?

Thank you all very much!