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Altera_Forum
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13 years ago

Help! Question about adder implementation!

Hi, I am try to build and test a very large adder, as my previous try have meet the quartus software constraints, my new way to do that is this: I write a basic logic for full adder, tha...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

In your top level you have asked for 6000 pins. I don't know of any fpga having this resource of pins.

Pins do not require LUTs but logic does. Anyway you are targetting an adder of two inputs 2000 bits wide. This is far too wide and will cover range 0 to 2^2000 which is is astronomically high.