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Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Help needed in VHDL Testbench

Hi all,

I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the dir_s is incremented only for one value ie. when fmcw_ramp_o >= fmcw_bw_i and for all other values its zero. Because of this, Ì am getting this error "wrong output: addition should take place". I don't know how to solve this problem.

I know for sure that dir_s should be 1 till it reaches the condition. I need to know how dir_s will be 1 continuously till fmcw_ramp_o< fstep_i or = "0000". The code looks like this: 

p_check_step: process(delayed_rst_s, clk_128meg_i)
 begin
   if (delayed_rst_s = '0') then
    dir_s <= '0';
    old_fmcw_ramp_s <= (others => '0');
   elsif (clk_128meg_i'event and clk_128meg_i = '0') then
     if (enable_i = '1' and fmcw_trig_i = '1') then
      if( dir_s = '0') then
        assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) + unsigned(fstep_i)) report " wrong output: addition should take place" severity error;
      else
        assert fmcw_ramp_o = std_logic_vector(unsigned(old_fmcw_ramp_s) - unsigned(fstep_i)) report " wrong output: subtraction should take place" severity error;
      end if;
      if (fmcw_ramp_o >= fmcw_bw_i) then
        dir_s <= '1';
      elsif (fmcw_ramp_o < fstep_i) then
        dir_s <= '0';
      elsif (fmcw_ramp_o = "000000000000000000000000") then
 dir_s <= '0';
      end if;
      old_fmcw_ramp_s <= fmcw_ramp_o;
      else
       dir_s <= '0';
       old_fmcw_ramp_s <= (others => '0');
     end if;
   end if;
  end process;

Also the VHDL code looks like this: 

begin
    if (reset_n_i = '0') then
      temp_s <= 0;
      cnt_s <= '0';
    elsif (clk_128meg_i'event and clk_128meg_i = '1') then
      if (enable_i = '1' and fmcw_trig_i = '1') then
        if (temp_s <= to_integer(unsigned(fstep_i))) then
   temp_s <= temp_s + to_integer(unsigned(fstep_i));   -- Accumulated values of temp_s and fstep_i
   cnt_s <= '0';
   elsif (temp_s = 0) then
    temp_s <= temp_s - to_integer(unsigned(fstep_i));
  cnt_s <= '0';
 elsif (temp_s >= (to_integer(unsigned(fmcw_bw_i)))) then
   temp_s <= temp_s - to_integer(unsigned(fstep_i));
   cnt_s <= '1';
 elsif (cnt_s = '0') then
   temp_s <= temp_s + to_integer(unsigned(fstep_i));   -- Up counter
 else
   temp_s <= temp_s - to_integer(unsigned(fstep_i));   -- Down counter
 end if;
      else
       temp_s <= 0;
       cnt_s <= '0';
      end if;
    end if;
  end process;

36 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    It could be the last else setting it back to zer:

    else

    dir_s <= '0';

    old_fmcw_ramp_s <= (others => '0');

    end if;

    end if;

    end process;
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    No this case is for the condition when enable and fmcw_trig '= '0' and since I am new to writing test benches in VHDL, can you help me to solve this problem. Thanks in advance

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    No this case is for the condition when enable and fmcw_trig '= '0' and since I am new to writing test benches in VHDL, can you help me to solve this problem. Thanks in advance

    --- Quote End ---

    I don't think this can be solved over here as you are best to know your logic. Have you tried looking at waveforms instead of just observing assertions
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Yes I tried checking the waveforms too. The problem is the dir_s is changing to 1 only for 1 value ie when fmcw_ramp>= fmcw_bw_i and dir_s should be 1 till the next condition fmcw_ramp < fstep_i. But it is not doing that. Please help me to solve this problem

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    Yes I tried checking the waveforms too. The problem is the dir_s is changing to 1 only for 1 value ie when fmcw_ramp>= fmcw_bw_i and dir_s should be 1 till the next condition fmcw_ramp < fstep_i. But it is not doing that. Please help me to solve this problem

    --- Quote End ---

    check your type as >,<,= may mislead you if std_logic

    also check that last statement is not to blame:

    elsif (fmcw_ramp_o = "000000000000000000000000") then

    try posting your waveforms (good quality)
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    I am using std_logic_vector and I think so the type is working well.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    your statement:

    elsif (fmcw_ramp_o < fstep_i) then

    dir_s <= '0';

    is likely the cause, you are comparing 10 bits with 24 bits??

    insert unsigned (or siged) around each

    after equalising size
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    I am using std_logic_vector and I think so the type is working well.

    --- Quote End ---

    std_logic_vector is not meant to represent arithmetic values, the types unsigned and signed are meant to do that.

    Unless you are using non-standard VHDL packages (like std_logic_unsigned/signed), if you are using std_logic_vector, then using >< or = will always fail if there is a missmatch in vector length.

    Instead of posting just a extract without the libraries for reference, it can be hard to understand the whole picture. Post the whole code so we can see the code in context.