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Altera_Forum's avatar
Altera_Forum
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9 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Yes I tried checking the waveforms too. The problem is the dir_s is changing to 1 only for 1 value ie when fmcw_ramp>= fmcw_bw_i and dir_s should be 1 till the next condition fmcw_ramp < fstep_i. But it is not doing that. Please help me to solve this problem

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check your type as >,<,= may mislead you if std_logic

also check that last statement is not to blame:

elsif (fmcw_ramp_o = "000000000000000000000000") then

try posting your waveforms (good quality)