--- Quote Start ---
I am using std_logic_vector and I think so the type is working well.
--- Quote End ---
std_logic_vector is not meant to represent arithmetic values, the types unsigned and signed are meant to do that.
Unless you are using non-standard VHDL packages (like std_logic_unsigned/signed), if you are using std_logic_vector, then using >< or = will always fail if there is a missmatch in vector length.
Instead of posting just a extract without the libraries for reference, it can be hard to understand the whole picture. Post the whole code so we can see the code in context.
Honored Contributor
