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Altera_Forum
Honored Contributor
10 years agoHelp needed in VHDL Testbench
Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum
Honored Contributor
10 years agoI am using std_logic_vector and I think so the type is working well.