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Altera_Forum's avatar
Altera_Forum
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10 years ago

Help needed in VHDL Testbench

Hi all, I have written the testbench file in such a manner that I need to perform updowncounting and downcounting based on the value of dir_s. But the problem is, when I execute the code, the di...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

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No this case is for the condition when enable and fmcw_trig '= '0' and since I am new to writing test benches in VHDL, can you help me to solve this problem. Thanks in advance

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I don't think this can be solved over here as you are best to know your logic. Have you tried looking at waveforms instead of just observing assertions