Help needed for implementing CRC polynomials in verilog

How about this: http://outputlogic.com/?page_id=321

Hi Manoj,

May refer to link below related to CRC Compiler User Guidehttps://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_crc.pdf

Also, a sample design of Nios II CRC Acceleration Design,

https://fpgacloud.intel.com/devstore/platform/10.0/Standard/nios-ii-crc-acceleration-design-example/

Thanks,

Regards