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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help me with this problem

Hi,

I want to create a project with Quartus II and its function is to enable three different leds deppending on a code. When you are entering the code, the first led will be ON. Depending on the code entered, the second or the third will be ON. My problem is, when the code is correct I want the second led to be ON 3 seconds, and if it's incorrect, the third led will be ON during 2 seconds. It would be great if you help me.

Thank you!

Notes: leds are declared as a Logic Vector and the numbers of the code are declared as interrup from 0 to 7.

Code: 


library IEEE;use IEEE.STD_LOGIC_1164.ALL;
ENTITY programa IS
PORT
(
interrup : in Std_Logic_Vector (7 downto 0);
clk, rst: in Std_Logic;
led : out Std_Logic_Vector (2 downto 0)
);
END programa;
ARCHITECTURE arch_programa OF programa IS
    type state is (zero, one, two, three, four, five, six);
    signal pr_state, nx_state : state;
    signal A : Std_Logic_Vector (3 downto 0);
BEGIN
    process(interrup, pr_state)
    begin
        case pr_state is
            when zero =>
                led <= "100";
                A(0) <= interrup(7);
                nx_state <= one;
            when one =>
                led <= "100";
                A(1) <= interrup(6);
                nx_state <= two;
            when two =>
                led <= "100";
                A(2) <= interrup(5);
                nx_state <= three;
            when three =>
                led <= "100";
                A(3) <= interrup(3);
                nx_state <= four;
            when four =>
                led <= "100";
                if(A = "1111") then nx_state <= five;
                else nx_state <= six;
                end if;
            when five =>
                led <= "010";
                nx_state <=zero;
            when six =>
                led <= "001";
                nx_state <=zero;
            end case;
    end process;
    
    process(rst,clk)
    begin
        if(rst='1') then
            pr_state <= zero;
        elsif (clk'event and clk = '1') then
            pr_state <= nx_state;
        end if;            
    end process;
    
end arch_programa;

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    You assume the bits of the code enters synchonoulsy with the fpga code. ok.

    I suggest write 2 components:

    a-One that turn on a LED when you put '1' on an input. Call it "trigger_a".

    b-turn on the third LED when you put '1' on input, called "trigger_b".

    This components act like monostables circuits. You can describe in vhdl:

    entity mono_led_2 is

    port(

    clk : in std_logic;

    n_clr : in std_logic;

    trigger_a : in std_logic;

    led_2 : out std_logic

    );

    end entity mono_led_2;

    The other entity is very similar. With a simple state machine and a counter you can do it.

    So, in the main code, the architecture "programa", when you reach the proper state to turn on the second LED, simply put '1' on trigger_a, and in the next state, put '0' on trigger_a to avoid retrigger:

    when zero =>

    trigger_a <= '0';

    trigger_b <= '0';

    led <= "100";

    A(0) <= interrup(7);

    nx_state <= one;

    when one =>

    led <= "100";

    A(1) <= interrup(6);

    nx_state <= two;

    when two =>

    led <= "100";

    A(2) <= interrup(5);

    nx_state <= three;

    when three =>

    led <= "100";

    A(3) <= interrup(3);

    nx_state <= four;

    when four =>

    led <= "100";

    if(A = "1111") then nx_state <= five;

    else nx_state <= six;

    end if;

    when five =>

    trigger_a <= '1';

    led <= "010";

    nx_state <=zero;

    when six =>

    trigger_b <= '1';

    led <= "001";

    nx_state <=zero;

    end case;

    You have to instantiate both components.