Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

Assuming the 100 MHz clock is driving the "upstream" and "downstream" devices this FPGA is connected to, you should have a separate virtual clock constraint and reference it in you set_input[output]_delay constraints and use derive_clock_uncertainty to get the most accurate uncertainties on I/O:

create_clock -name clock_in_vir -period 10

create_clock -name clock_out_vir -period 10

set_input_delay -clock clock_in_vir ...

set_output_delay -clock clock_out_vir ...

Aside from that, looking at the timing reports, these failures seem to be feedback loops in your design. I'm not sure why you have such loops, but it might be useful to look back at your code to try to understand them. You can cross-probe from the timing reports by right-clicking a failing timing path and select Locate Path. It might be helpful to see these paths in the Technology Map Viewer to understand what they're connected through and what they're doing.