Hello, In my design I keep getting hold time violation warnings. "From Node" and "To Node" in the TimeQuest indicate the same signal.

One way to resolve Hold issues, is to phase shift your clock. If the design uses a PLL, then you can phase shift the clock by a few degrees and see if the hold violations are resolved. I had a similar kind of issue with Hold violations in my Qsys design. I then shifted the generated clocks by 90 and re-compiled and the hold violations were gone, did see a better slack margin as well as Fmax of the design also went up.