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CATHA2's avatar
CATHA2
Icon for New Contributor rankNew Contributor
7 years ago

Hello, I am new to Altera and Quartus and I needed help. I'm using Altera EPM3032ATC44-10 on my hardware development board. I have Quartus II 13.0.

Hello, I am new to Altera and Quartus and I needed help. I'm using Altera EPM3032ATC44-10 on my hardware development board. I have Quartus II 13.0. I wrote a code in VHDL for one of my company's p...
ak6dn's avatar
ak6dn
Icon for Regular Contributor rankRegular Contributor
7 years ago

That is just about a bare minimum .sdc configutation for the clock, input, and output timing.

When you compile, does the Quartus timing analyzer indicate any timing errors?

Do you have a simpler source design file you can use to simulate and then verify in your hardware?

Do you know your hardware board is operating without error? Do you have another board to try and see if the behavior is the same?

CATHA2's avatar
CATHA2
Icon for New Contributor rankNew Contributor
7 years ago

The timing analyzer does not give me an error, but I get a warning which says .sdc file is missing. The code gets compiled just fine.

There is no issue with the hardware board since we are writing a new source code (modified from the original source code with minor modifications) on the old hardware which works fine.